A content addressable memory (CAM) is a storage device that stores data in a number of cells which can be accessed or loaded on the basis of their contents. A CAM can be used to store and access data according to address location and also determine the address location of presented data. These operations are write, read and search, respectively. The memory can be made more powerful by incorporating additional logic whereby a "don't care" state, as well as the "one" and "zero" states can be presented to the CAM so that certain bits can be masked from the search operation.
All cells are compared simultaneously in parallel, and a single mismatch on any of the cells signals a mismatch for the entire word. With the parallel approach, the data must be stored such that a search operation will not destroy it. The data should be stored on an active device in such a way that when a "mismatch" is presented, the device changes its output while retaining its state.
The storage can be achieved in a number of ways. However, field effect transistor technology is most attractive when density, speed, power dissipation and cost are taken into account.
In prior art CAM cell design there are two bit lines that run through all words in the memory. Those bit lines are used both to carry data to be written into the cells and to present data against which a match is to be made. A Match line runs through the memory connecting an entire word and serves as a wired-OR for mismatches. If any cell in the word mismatches the presented data, the Match line is discharged to a lower potential. The following are several examples of prior art content addressable memory systems capable of high speed operation.
U.S. Pat. No. 3,969,707 to Lane et al. teaches a content addressable memory having a cell with a pair of current switches one at each output to provide for searching the cell at high speed and without disturbing the contents of the cell. The patent does not teach a content addressable memory having reduced power consumption and high speed switching as a result of the improved circuits of the present invention.
An article in the IBM Technical Disclosure Bulletin, Volume 26, Number 10B, March 1984, at page 5364 by Schuster describes a dynamic content addressable memory with refresh feature. The publication presents a space efficient content addressable memory cell which uses five active devices. However, the publication does not teach nor suggest a content addressable memory having high speed switching devices or reduced power consumption as does the present invention.
U.S. Pat. No. 4,646,271 to Uchiyama et al. shows a content addressable memory having dual access modes. The patent basically teaches the use of a single array of cells as either a content addressable memory or a random access memory depending upon which word selection line is activated. The patent does not teach nor suggest increasing switching speed nor reducing power consumption of the content addressable memory as is taught and claimed by the present invention.
U.S. Pat. No. 4,831,585 to Wade et al. teaches a four transistor cross-coupled bit line content addressable memory. The patent describes a content addressable memory cell and the structure thereof in which cross coupling results in reduced degenerative capacitive coupling which improved speed and noise immunity of the cell. However, the content addressable memory of the patent does not teach or suggest how power consumption may be reduced in a content addressable memory as does the present invention.
An article in the IBM Technical Disclosure Bulletin, Volume 32, Number 3A, August 1989, at page 478 by Lipa et al. describes a high performance static content addressable memory cell which has certain similarities to the content addressable memory according to the present invention. However, although the article addresses speed considerations with respect to discharge of the Match line, the article does not teach or suggest reduced power consumption by preventing current flow on a miscompare as does the present invention.
The prior art content addressable memories described above, while attempting to provide solutions to a number of problems in content addressable memory design, such as simplification of design or improved switching speeds by reducing load capacitance, do not provide the combination of improved features of the present invention.